The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
In a high speed serial communication link, such as the lanes of a 10 Gigabit (10 G) or 100 Gigabit (100 G) Ethernet connection, a transmitter transmits a data signal into a communication channel (channel) without an accompanying clock signal. The data signal includes a sequence of symbols, each symbol carrying information from some number of bits, such as one, two, or more bits, or in some cases tractions of bits. The data is transmitted at a rate determined by a transmission (Tx) clock signal.
In order to receive the data on the communication link, a receiver determines a phase and a frequency of a clock used to sample a signal received from the channel. The process of determining the phase and frequency of the clock is part of a Clock and Data Recovery (CDR) process. The CDR process typically uses a circuit including a Delay Locked Loop (DLL).
A DLL generates an output signal having a specified phase relationship with an input signal. For example, the DLL may be used to produce the output signal having a transition occurring at a delay from a transition of the input signal equal to a quarter, a half, or three-quarters of a clock period of the input signal. The input signal typically includes a clock signal.
The DLL includes one or more variable delay line circuits that are used to generate the output signal by delaying the input signal. The delay produced by the one or more delay line circuits is controlled according to a phase detect signal produced by a phase detect circuit.